Generally, when a memory cell in a Static Random Access Memory (SRAM) enters a standby mode, to reduce the leakage current, the operational voltage of the memory is reduced to a voltage sufficient to retain the data, commonly called the “retaining voltage.” In many approaches, the power management circuitry that controls the retaining voltage is implemented by logic devices that need area overheads and that do not work well with devices manufactured by a memory process. For example, in an approach, the SRAM retaining voltage is generated by a diode connected logic device. Because SRAMs and logic devices have different manufacturing process variations, the retaining voltage while functioning for the logic device can cause loss of data in the SRAM. In another approach, the retaining voltage is generated by a voltage regulator, which requires a longer wake up time and consumes lots of power. In another approach, the SRAM edge cell requires a large die area for a short bit line in segmented SRAMs and register files.
Like reference symbols in the various drawings indicate like elements.